<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>CPU on PeriPragmaton</title><link>https://peripragmaton.com/tags/cpu/</link><description>Recent content in CPU on PeriPragmaton</description><generator>Hugo</generator><language>en</language><copyright>&amp;copy; 2026 PeriPragmaton</copyright><lastBuildDate>Sat, 17 Oct 2026 20:54:24 +0000</lastBuildDate><atom:link href="https://peripragmaton.com/tags/cpu/index.xml" rel="self" type="application/rss+xml"/><item><title>Under Pressure: Mind the Instruction Cache</title><link>https://peripragmaton.com/posts/icache-pressure/</link><pubDate>Sat, 17 Oct 2026 20:54:24 +0000</pubDate><guid>https://peripragmaton.com/posts/icache-pressure/</guid><description>What happens when a hot loop runs through more code than the instruction cache can hold, and why batching work is a design decision the compiler won&amp;rsquo;t make for you.</description></item><item><title>Quirks of a CPU: Cache Aliasing</title><link>https://peripragmaton.com/posts/cache-aliasing/</link><pubDate>Sun, 11 Oct 2026 19:43:59 +0000</pubDate><guid>https://peripragmaton.com/posts/cache-aliasing/</guid><description>Summing a power-of-two-sized matrix column by column is eight times slower than the same loop with one extra element per row. Why cache sets make some addresses collide, and how to spot it.</description></item></channel></rss>